In this work, the designs of both non-iterative and iterative approximate logarithmic multipliers (LMs) are studied to further reduce power consumption and improve performance. Non-iterative approximate LMs (ALMs) that use three inexact mantissa adders, are presented. The proposed iterative approximate logarithmic multipliers (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approximate mirror adders for the final addition. Error analysis and simulation results are also provided; it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve a higher accuracy and lower power consumption than conventional LMs using exact units. Compared with conventional LMs with exact units, the normalized mean error distance (NMED) of 16-bit approximate LMs is decreased by up to 18% and the power-delay product (PDP) has a reduction of up to 37%. The proposed approximate LMs are also compared with previous approximate multipliers; it is found that the proposed approximate LMs are best suitable for applications allowing larger errors, but requiring lower energy consumption and low power. Approximate Booth multipliers fit applications with less stringent power requirements, but also requiring smaller errors. Case studies for error-tolerant computing applications are provided.

The collaboration between humans and robots is one of the most disruptive and challenging research areas. Even considering advances in design and artificial intelligence, humans and robots could soon ally to perform together a number of different tasks. Robots could also became new playmates. In fact, an emerging trend is associated with the so-called phygital gaming, which builds upon the idea of merging the physical world with a virtual one in order to let physical and virtual entities, such as players, robots, animated characters and other game objects interact seamlessly as if they were all part of the same reality. This paper specifically focuses on mixed reality gaming environments that can be created by using floor projection, and tackles the issue of enabling accurate and robust tracking of off-the-shelf robots endowed with limited sensing capabilities. The proposed solution is implemented by fusing visual tracking data gathered via a fixed camera in a smart environment with odometry data obtained from robot's on-board sensors. The solution has been tested within a phygital gaming platform in a real usage scenario, by experimenting with a robotic game that exhibits many challenging situations which would be hard to manage using conventional tracking techniques.

Software for computer animation is generally characterized by a steep learning curve, due to the entanglement of both sophisticated techniques and interaction methods required to control 3D geometries. This paper proposes a tool designed to support computer animation production processes by leveraging the affordances offered by articulated tangible user interfaces and motion capture retargeting solutions. To this aim, orientations of an instrumented prop are recorded together with animator's motion in the 3D space and used to quickly pose characters in the virtual environment. High-level functionalities of the animation software are made accessible via a speech interface, thus letting the user control the animation pipeline via voice commands while focusing on his or her hands and body motion. The proposed solution exploits both off-the-shelf hardware components (like the Lego Mindstorms EV3 bricks and the Microsoft Kinect, used for building the tangible device and tracking animator's skeleton) and free open-source software (like the Blender animation tool), thus representing an interesting solution also for beginners approaching the world of digital animation for the first time. Experimental results in different usage scenarios show the benefits offered by the designed interaction strategy with respect to a mouse \& keyboard-based interface both for expert and non-expert users.

This is the beginning of the year EiC update on the IEEE Transactions on Computers

This installment of Computer's series highlighting the work published in IEEE Computer Society journals comes from IEEE Transactions on Computers.

In this paper we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to ceil(n/4) for n = 64-bit unsigned operands. This is in contrast to the conventional maximum height of ceil((n + 1)/4). Therefore a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multi- pliers, combined signed/unsigned multipliers, and other values of n.

Computer-supported assessment tools can bring significant benefits to both students and teachers. When integrated in traditional education workflows, they may help to reduce the time required to perform the evaluation and consolidate the perception of fairness of the overall process. When integrated within on-line intelligent tutoring systems, they could provide students with a timely feedback and support self-assessment activities. The current work presents an alternative approach (and not just a \"yet-another-implementation\") to the problem of automatically evaluating technical skills needed to create 3D computer animations. Although some solutions have been reported already in the literature, their applicability is partially constrained, as they require the teaching staff to define evaluation criteria that are strictly linked to the particular animation technique being assessed. Students are forced to operate in environments where they can only perform a part of the required animation steps, by using a pre-defined set of techniques and tools. To address such limitations, the proposed system exploits shape- and time-based features extracted from the 3D point clouds (i.e., the set of data points) describing animated geometries, which are independent of the particular animation techniques used. Experimental observations collected in the evaluation of course assignments in which students were asked to recreate 3D animations of deformable meshes prepared by the teaching staff showed a good correlation between automatic and manual evaluations. Obtained results confirmed the ability of the proposed approach to cope with heterogeneous evaluation tasks in which the relevant learning outcomes can be properly considered.

This is the state of the journal editorial for 2017, summarizing the results obtained in 2016 and presenting the new initiatives for 2017

A spotlight on the IEEE Transactions on Computers, on Computer Arithmetic and its impact.

A recent trend in human-computer interaction is to ease the creation of content such as apps and games via intelligent systems, allowing nonskilled users to define a given system's behavior through visual programming or simplified metalanguages. However, when the number of elements to be controlled increases, the complexity could become comparable to that of traditional coding strategies. This article addresses this issue by proposing a framework for automatically configuring a system's behavior based on user input and context information. Framework effectiveness has been tested in a game-creation scenario and used for automatically mapping user commands on virtual character actions based on a natural language description of the game scene. The use of semantics-based mapping reduces the effort and complexity linked with the configuration of the interaction logic, thus decreasing the number of commands needed for controlling the characters. The Web extra includes the questionnaire and full catalogue of descriptions collected

In this paper the Editor-in-Chief of the IEEE Transactions on Computers, both presents the state of the journal after (almost) the completion of the first year since the beginning of his term, and introduces the new Associate Editors

This is the July report on the state of the IEEE Transactions on Computers

Rationale: Omalizumab, an anti-IgE monoclonal antibody, is indicated in adults with severe persistent allergic asthma. Exhaled molecular markers can provide phenotypic information in asthma. Objectives: Determine whether adults with severe asthma on omalizumab (anti-IgE+) have a different breathprint compared with those who were not on anti-IgE therapy (anti-IgE-) as assessed by eNoses and gas chromatography/mass spectrometry (GC/MS) (breathomics). Methods: This was a cross-sectional analysis of the U- BIOPRED adult cohort. Severe asthma was defined by IMI-criteria [Bel, Thorax 2011]. Anti-IgE+ patients were on a regular treatment with s.c. omalizumab (150-375 mg) every 2-4 weeks. Exhaled volatile compounds trapped on adsorption tubes were analysed by a centralized eNose platform (Owlstone Lonestar, two Cyranose 320, Comon Invent, Tor Vergata TEN), including a total of 190 sensors, and GC/MS. Recursive feature elimination (http://topepo.github.io/caret/rfe.html) was used for feature selection and random forests, more robust to overfitting, for classification. Results: 9 anti- IgE+ (females/males 2/7, age 52.6±16.3 years, mean±SD, 1/2/6 current/ex/nonsmokers, pre-bronchodilator FEV1 70.6±21.1% predicted value) and 30 anti-IgE- patients (18/12 females/males, age 53.2±14.2 years, 0/16/14 current/ex/nonsmokers, pre-bronchodilator FEV1 59.6±30.7% predicted value) were studied. Conclusions: Preliminary results suggest that breathomics can distinguish between anti-IgE+ and anti-IgE- severe asthma patients.

Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation (as measured by the error rate and the so-called normalized error distance) can be met with respect to circuit-based figures of merit of a design (number of transistors, delay and power consumption). Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Wallace multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented. The results show that the proposed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs provide excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio (more than 50 dB for the considered image examples)

This is the welcome message from the incoming Editor-in-Chief (EiC) of the IEEE Transactions on Computers. For the first time in 64 years of life of the IEEE Transactions on Computers, a Researcher from Continental Europe has been appointed to serve as EiC

Robustly and efficiently tracking pedestrians in the infrared spectrum is a crucial requirement for a number of applications. At the same time, it is also particularly critical due to both the peculiarities of infrared images and pedestrian targets. In fact, low resolutions and high signal-to-noise ratios combined with extremely variable target signatures, chaotic trajectories, and frequent occlusions have forced researchers to develop ever more complex strategies characterized by a neat trade-off between tracking accuracy and computational complexity. Thus, most of the existing techniques might not be capable of ensuring real-time performances with a suitable degree of robustness, especially on limited-resource hardware used, e.g., in automotive or security scenarios. We present a technique that extends an extremely efficient tracking method originally tailored to targets that exhibit a clear and stable hot spot to allow it to deal with pedestrian targets by reusing its core components and integrating an occlusion detection and recovery mechanism. Experimental results obtained on public datasets confirmed that the devised method is able to obtain a robustness that is superior to that of other common approaches by maintaining the high tracking speed of the reference method

This installment of Computer's series highlighting the work published in IEEE Computer Society journals comes from the IEEE Transactions on Computers

In this paper the Editor-in-Chief of the IEEE Transactions on Computers, presents the state of the journal after 5 months since the beginning of his term, as well as introduces the new Associate Editors

Memories are one of the most critical components of many systems: due to exposure to energetic particles, fabrication defects and aging they are subject to various kinds of permanent and transient errors. In this scenario, Unequal Error Protection (UEP) techniques have been proposed in the past to encode stored information, allowing to detect and possibly recover from errors during load operations, while offering different levels of protection to partitions of codewords according to their importance. Low-Density Parity-Check (LDPC) codes are used in many communication standards to encode the transmitted information: at reception, LDPC decoders heavily rely on memories to store and correct the received information. To ensure efficient and reliable decoding of information, the need to protect the memories used in LDPC decoders is of primary importance. In this paper we present a study on how to efficiently design UEP techniques for LDPC decoder memories. The devised UEP method is divided in four adjustable levels, each one offering a different degree of protection. The full UEP, along with simplified versions, has been implemented within an existing decoder and its area occupation and power consumption evaluated. Comparison with the literature on the subject shows an unmatched level of protection from errors at a small complexity and energy cost

Motion capture systems provide an efficient and interactive solution for extracting information related to a human skeleton, which is often exploited to animate virtual characters. When the character cannot be assimilated to an anthropometric shape, the task to map motion capture data onto the armature to be animated could be extremely challenging. This paper presents two methodologies for the automatic mapping of a human skeleton onto virtual character armatures. Kinematics chains of the human skeleton are analyzed in order to map joints, bones and end-effectors onto an arbitrary shaped armatures. Both forward and inverse kinematics are considered. A prototype implementation has been developed by using the Microsoft Kinect as body tracking device. Results show that the proposed solution can already be used to animate truly different characters ranging from a Pixar-like lamp to different kinds of animals

The ever more complex labor world and the current economic crisis ask learners and workers to continuously update their qualification level to stay relevant on the market. Hence, education and training providers need to adjust their offer in order to cope with such evolving requirements. However, because of the huge number of variables to consider, finding the right learning content able to let an individual fill his/her competency gap may be a task hard to accomplish. In this paper we propose a semantic-based recommender system that is designed to cross heterogeneous information about learners' and workers' background as well as advertised job positions with a catalogue of online courses in order to identify the most appropriate learning resources. Experimental observations showed a good agreement between human and automatic recommendations, confirming the applicability of the emerging semantic technology to the generation of user-centered services capable to adapt to individual's learning needs

As technological, economic, and social factors drive scientific publishing toward electronic formats, opportunities open beyond traditional reading and writing frameworks. Journal articles now, and in the future, can increasingly include a variety of supplemental multimedia and interactive materials for augmented reading that will impact both the nature and presentation of scientific research. The IEEE Computer Society is preparing for this evolution

Augmented reality (AR) is a well-known technology that can be exploited to provide mass-market users an effective and customizable support in a large spectrum of personal applications, by overlapping computer-generated hints to the real world. Mobile devices, such as smartphones and tablets, are playing a key role in the exponential growth of this kind of solutions. Nonetheless, there exists some application domains that just started to take advantage from the AR systems. Maintenance, repair, and assembly have been considered as strategic fields for the application of the AR technology from the 1990s, but often only specialists using ad hoc hardware were involved in limited experimental tests. Nowadays, AR-based maintenance and repair procedures are available also for end-users on consumer electronics devices. This paper aims to explore new challenges and opportunities of this technology, by also presenting the software framework that is being developed in the EASE-R3 project by exploiting reconfigurable AR procedures and tele-assistance to overcome some of the limitations of current solutions

Rationale: Some severe asthma patients require oral corticosteroids (OCS) likely due to greater disease severity. Exhaled molecular markers can provide phenotypic information in asthma. Objectives: Determine whether patients on OCS (OCS+) have a different breathprint compared with those who were not on OCS (OCS-); determine the classification accuracy of eNose as compared to FEV1 % pred, % sputum eosinophils, and exhaled nitric oxide (FENO). Methods: This was a cross-sectional analysis of the U-BIOPRED cohort. Severe asthma was defined by IMI-criteria [Bel Thorax 2011]. OCS+ patients had daily OCS. OCS- patients had never had OCS and were on maintenance inhaled fluticasone equivalent >1000 μg/day. Exhaled volatile organic compounds trapped on adsorption tubes were analysed by centralized eNose platform (Owlstone Lonestar, Cyranose 320, Comon Invent, Tor Vergata TEN) including a total of 190 sensors. t test was used for comparing groups and support vector machine with leave-one-out cross-validation as a classifier. Results: 33 OCS+ (age 55±11yr, mean±SD, 52% female, 27% smokers, pre-bronchodilator FEV1 64.1±24% pred) and 40 OCS- severe asthma patients (age 54±15yr, mean±SD, 55% female, 35% smokers, pre-bronchodilator FEV1 61.8±24% pred) were studied. Sensor by sensor analysis showed that 56 sensors provided different mean values (change in sensor resistance or frequency) between groups (P<0.05). Accuracy of classification was as follows: eNose 71% (n=73), FENO 71% (n=70), FEV1 62% (n=73) and sputum eosinophils 59% (n=37). Conclusions: Preliminary results suggest OCS+ and OCS- severe asthma patients can be distinguished by an eNose platform

Recently, indoor navigation on mobile devices has received attention from both startups and large vendors, since it has many relevant practical and commercial applications. User positioning and navigation using GPS signals is becoming more and more popular, mainly due to the increasing availability of acceptable quality sensors into low-cost consumer devices as smartphones. However, indoor GPS-navigation is highly unreliable because of the poor communication with satellites and the lack of detailed maps. In this paper we discuss the technologies allowing the indoor computation of accurate location and orientation data, as well as other issues and challenges that indoor navigation apps should cope with. In particular, we present and make explicit reference to a system for indoor navigation (running on a smartphone), which has been designed by the Authors, including the main problems that have been tackled during its implementation

This survey of current job search and recruitment tools focuses on applying a computer-based approach to job matchmaking. The authors present a semantic-based software platform, LO-MATCH - developed in the framework of a European project on lifelong learning - that highlights future research directions. There are three related Web extras that provide supplemental material

When moving in generic indoor environments, robotic platforms generally rely solely on information provided by onboard sensors to determine their position and orientation. However, the lack of absolute references often leads to the introduction of severe drifts in estimates computed, making autonomous operations really hard to accomplish. This paper proposes a solution to alleviate the impact of the above issues by combining two vision‐based pose estimation techniques working on relative and absolute coordinate systems, respectively. In particular, the unknown ground features in the images that are captured by the vertical camera of a mobile platform are processed by a vision‐based odometry algorithm, which is capable of estimating the relative frame‐to‐frame movements. Then, errors accumulated in the above step are corrected using artificial markers displaced at known positions in the environment. The markers are framed from time to time, which allows the robot to maintain the drifts bounded by additionally providing it with the navigation commands needed for autonomous flight. Accuracy and robustness of the designed technique are demonstrated using an off‐the‐shelf quadrotor via extensive experimental tests

The modular exponentiation on large numbers is computationally intensive. An effective way for performing this operation consists in using Montgomery exponentiation in the Residue Number System (RNS). This paper presents an algorithmic and architectural study of such exponentiation approach. From the algorithmic point of view, new and state-of-the-art opportunities that come from the reorganization of operations and precomputations are considered. From the architectural perspective, the design opportunities offered by well-known computer arithmetic techniques are studied, with the aim of developing an efficient arithmetic cell architecture. Furthermore, since the use of efficient RNS bases with a low Hamming weight are being considered with ever more interest, four additional cell architectures specifically tailored to these bases are developed and the tradeoff between benefits and drawbacks is carefully explored. An overall comparison among all the considered algorithmic approaches and cell architectures is presented, with the aim of providing the reader with an extensive overview of the Montgomery exponentiation opportunities in RNS.

The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2(n)-tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication

The rapid growth in the number of conferences and papers appearing in conference proceedings publications has increased the need to examine the issue of conference paper quality. Since conference content is included in permanent repositories, such as IEEE's Xplore, the existence of low-quality papers in a conference will degrade the value and reputation of the conference and the repository. The aim of this contribution is to consider these issues from the point of view of the Conference Publications Operations Committee of the IEEE Computer Society, and offer ideas that could lead to improved conference publishing quality for all IEEE societies and even non-IEEE entities

A radix-2 digit-recurrence algorithm and architecture for the computation of the cube root are presented in this paper. The original recurrence based on the concept of completing the cube is modified to allow an efficient implementation of the algorithm and the cycle time and area cost of the resulting architecture are estimated as 7.5 times the delay of a full adder and around 9,000 nandl cells, respectively, for double-precision computations

A general digit-recurrence algorithm for the computation of the mth root (with an m integer) is presented in this paper. Based on the concept of completing the mth root, a detailed analysis of the convergence conditions is performed and iterationindependent digit-selection rules are obtained for any radix and redundant digit set. A radix-2 version for mth rooting is also studied, together with closed formulas for both the digit selection rules and the number of bits required to perform correct selections

In this paper, we propose a class of division algorithms with the aim of reducing the delay of the selection of the quotient digit by introducing more concurrency and flexibility in its computation. From the proposed class of algorithms, we select one that moves part of the selection function out of the critical path, with a corresponding reduction in the critical path compared with existing alternatives. We present the algorithm and describe the architectures for radix 4 and for radix 16. For radix 16, we use the scheme of overlapping two radix-4 stages. In both cases, radix 4 and radix 16, we show that our algorithms allow the design of units with well-balanced critical paths with consequent decreases of the cycle times. Moreover, in the radix-16 case, we include some additional speculation techniques. To estimate the speedup, we used a rough timing model based on logical effort. For both radices, we estimate a speedup of about 25 percent with respect to previous implementations. In the radix-4 case, this is achieved by using roughly the same area, while, in the radix-16 case, the area is increased by about 30 percent. We verified our estimations by performing a synthesis of the radix-4 units.

Block motion estimation represents a cpu-intensive task in video encoding and many fast algorithms have been developed to improve the searching and matching phases. A milestone within the lossless approach is partial distortion elimination (PDE/SpiralPDE) in which distortion is the difference between the block to be coded and the candidate prediction block. In this paper we show that contributions to distortion can be reliably estimated using the Taylor series expansion. The approximation method is then used to derive eight new PDE-based algorithms in which the matching order depends on the magnitude of the estimated distortion contributions. Exhaustive comparisons using several, widely different, video sequences show that these algorithms reduce the total encoding time by up to 20% with respect to SpiralPDE, while the computation for motion estimation is reduced by about 30%. The proposed algorithms are also compared with other PDE-based lossless approaches known in literature and there is a significant gain over all of them

An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists of increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor or the delay of an iteration. As a consequence, for some values of the effective radix, it permits an implementation with a smaller area and the same execution time of the original scheme. Details of the algorithm and the implementation are presented. Estimations of the execution time and area are given for 54 bit and 114 bit quotients and compared with those of other division units

The visualization of dense vector fields has important applications for scientific purposes. Beyond the standard methods, such as arrows and particle tracing, texture-based methods are able to show almost all the details of a field. This paper presents the Thick Oriented Stream-Line (TOSL) algorithm, which can show direction, orientation and local flow speed even for dense vector fields by simulating the convolution process. A practical comparison of the performances of TOSL vs. other visualizations algorithms (LIC and fastLIC) shows that the proposed algorithm can provide output textures faster than the other considered techniques.

An algorithm for square root with prescaling and selection by rounding is developed and combined with a similar scheme for division. Since division is usually more frequent than square root, the main concern of the combined implementation is to maintain the low execution time of division, while accepting a somewhat larger execution time for square root. The algorithm is presented in detail, including the mathematical development of bounds for the first square-root digit and for the scaling factor. The proposed implementation is described, evaluated and compared with other combined div/sqrt units. The comparisons show that the proposed scheme potentially produces a significant speed-up for division, whereas, for square root, the speed-up is small

his paper presents a new algorithm to generate ray-cast CSG animation frames. We consider sequences of frames where only the objects can move; in this way, we take advantage of the high screen area coherence of this kind of animation. A new definition of bounding box allows us to reduce the number of pixels to be computed for the frames after the first. We associate a CSG subtree and two new flags, denoting if the box has changed in the current frame and if it will change in the next frame, with each box. We show with three examples the advantages of our technique when compared with an algorithm which entirely renders each frame of an animation. Intersections with CSG objects may be reduced to about one-fifth, while the rendering may be computed up to four times faster for the test sequences

The generation of 3-D solid objects, and more generally solid geometric modelling, is very important in Computer Aided Design (CAD). An important role is played by the Constructive Solid Geometry (CSG) representation scheme. IN CSG, objects are described by trees of Boolean operations on half-spaces or boundaries of primitive solids. The study of techniques to speed up the rendering of scenes modelled with the CSG scheme is an attractive field of research; in this paper we propose a new algorithm which reduces the computational complexity for ray casting approaches. Our strategy identifies a set of areas on the plane of view where the rays starting from the observer have to be traced; for each zone, only a portion of the entire CSG tree has to be considered for intersection tests, instead of the whole database of the primitive objects. A comparison of our algorithm with a ray caster that adopts bounding volume hierarchies and with a freeware ray tracer called POV-Ray shows that, for the examples considered, we may reduce the intersection tests to one third of those performed when standard optimizations are adopted.

Carry-save multipliers require an adder at the last step to convert the carry-sum representation of the most significant half of the result into a non-redundant form. This paper presents n×n multiplication schemes where this conversion is performed with a circuit operating in parallel with the carry-save array. The most relevant feature of the proposed multipliers is that the full 2n-bit result is produced, unlike similar multiplication schemes presented in the literature

The authors present a parallel algorithm for fast rendering. A set of zones which can be concurrently processed is identified; this set is split into a number of subsets equal to the number of available processors. Each processor renders, in parallel with the others, a zone of its set

The paper analyses an SRT radix-B division algorithm where the determination of the quotient digits is performed in parallel with the updating of the residual. The authors do not use any prescaling digit prediction (in order to reduce the complexity of the selection function) as it is done using other prediction-based techniques. The authors present application examples of radix-2 (and radix-4, briefly) division design using their prediction scheme, and compare them with the `classical' SRT radix-2, radix-4 and radix-16 schemes without prediction. They estimate that the proposed algorithm achieves execution times comparable to the computation delay of the `classical' SRT radix-B 2 division algorithm without prediction, but requires less hardware

In a previous paper by P. Montuschi and L. Ciminiera (ibid., vol. 42, no.2 p239-246, Feb 1993), an architecture for shared radix 2 division and square root has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteristics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, which has the benefit to further reduce the computation delay with respect to the time estimated in that work

Several computer graphics algorithms (such as ray-tracing) heavily relate their performances to the efficiency of the tests of intersection between the rays of a light source and the objects of a synthetic scene. Some solid modelling and robotics algorithms need also to test quickly the possible interferences of the different parts of a system such as the arms of different robots. To speed-up the test, the free shape objects to be tested are encapsulated into boxes and the test starts by performing a check on overlapping of the bounding boxes, thus producing a section of the space where an intersection can occur. Successively, if the boxes overlap, the test continues on the original free shape objects, but only in the portion of the 3D-space resulting from the first step. The authors present a simple, fast and efficient algorithm (called the `bounding boxes group' method) to compute a tight bounding entity of a complex object modelled in the constructive solid geometry (CSG). If no upper limit is set to the number of elements of each bounding box group, the algorithm is shown to achieve the tightest possible solution. Algorithms are also presented which allow a reduction of the number of bounding elements but still provide a satisfactory and tight encapsulation

The advantages of the convergence with the square of the Newton-Raphson method are combined with the precision characteristics of digit-by-digit algorithms to obtain units for fast division that satisfy the IEEE 754 floating point standard requirements. A general design methodology that leads to a class of alternative architectures providing interesting performances for division is presented, together with one example of possible implementation. In particular, the proposed implementation achieves a speedup varying from 20% to about 30% in comparison with a previous architecture by Fandrianto, with a relatively small additional hardware cost if a multiplier is already available on the arithmetic unit

Over-redundant digit sets are defined as those ranging from -s to +s, with s⩾B, B being the radix. This paper presents new techniques for the direct computation of division, that use an over-redundant digit set for representing the quotient, instead of simply redundant ones used previously. In particular, general criteria for synthesizing the digit selection rules and remainder updating are given for any radix and index of redundancy. A methodology combining the use of over-redundant digit sets with the prescaling of the divisor is also studied in order to achieve radix-B division units with trivial digit selection functions. It is also shown, for the specific case of radix-4 that using a prescaling slightly wider than in a radix-4 unit by M.D. Ercegovac and T. Lang (1990) possible to avoid the digit selection table. The paper also presents a modified algorithm for on-the-fly conversion of the result into the irredundant form. The proposed methodology can be considered as an alternative to existing division techniques

We present a radix-8 divider that uses an over-redundant digit set for the quotient in order to obtain simple digit selection rules. We show that the proposed enlarged set of values for the quotient digit does not lead to increases both in the complexity and the delay of the adder required to update the remainder, with respect to similar solutions, since the values allowed for the quotient digit have been selected carefully. The digit selection process is subdivided into two concurrent steps, each one making reference to a secondary digit set and the resulting implementation can be cheaper and faster than other units which do not use over-redundant digit sets. A performance analysis estimates a speed improvement from 25% to 35% with respect to a radix-8 architecture by Fandrianto, and from 21% to 30% with respect to a radix-4 architecture with prescaling, presented by Ercegovac and Lang. As required from the IEEE 754 floating point standard, the proposed algorithm features the correct remainder of the division.

A division algorithm in which the quotient-digit selection is performed by rounding the shifted residual in carry-save form is presented. To allow the use of this simple function, the divisor (and dividend) is prescaled to a range close to one. The implementation presented results in a fast iteration because of the use of carry-save forms and suitable recodings. The execution time is calculated and several convenient values of the radix are selected. Comparison with other dividers for radices 2^9 to 2^18 is performed using the same assumptions

A new architecture is presented for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the remainder is not updated, and the subsequent tradeoff is presented. The proposed architecture is also extended in order to consider other implementations

A radix 4 division architecture is presented which partially overlaps the updating of the remainder with the digit selection procedure. It is obtained by separating the radix 4 digit selection process into two concurrent substeps. The proposed unit requires a simple selection table and involves a small extra expense for the additional hardware compared to the usual radix 4 division units. Four possible implementations are derived from the general model, with different types of substeps. The high level evaluation shows that the proposed architectures offer an efficient alternative

A scheme for performing higher radix square root based on prescaling of the radicand is presented to reduce the complexity of the result-digit selection. The scheme requires several steps, namely multiplication for prescaling the radicand, square root, multiplication for prescaling for the division, and division. Online algorithms are used to reduce the overall time and pipelining to reuse the different modules. An estimate of the execution time for a radix-256 unit for double-precision square root and a comparison with other implementations indicate that the proposed approach is an alternative to consider when designing a square-root unit

A general approach for designing units for higher-radix division is outlined which is based on several subunits operating in parallel. A lower-radix-division unit is used as the building block of the architecture, and the division step is split into two phases which are carried out in parallel. It is shown that the proposed architecture permits the design of units for higher-radix division with digit-selection tables requiring only few supplementary input bits with respect to the tables used by lower-radix division systems.

Timed token protocols have increased in importance with the growth of local area network (LAN) communications One of the most important timed token protocols is certainly IEEE 802.4, a standard given the name 'token bus', which represents one of the most interesting solutions to the problem of handling, on the same physical channel, the transmission of messages belonging to multiple priority classes. In the paper, the authors study some time characteristics of the IEEE 802.4 protocol, giving bounds to the mean and the maximum duration of a complete token cycle. It is shown how these results can be conveniently used by a network designer to tune the parameters that characterise an IEEE 802.4 local area network

The problem of obtaining optimal starting values for the calculation of square root using Newton-Raphson's Method is considered. This paper presents the best starting values theory in order to optimize the maximum absolute error after a given number of iterations. Two different methods are shown, and a third, which can be considered as a mixture of the previous two, is briefly discussed. The approach combines analytical and numerical methodologies, which gives more interesting results on the main characteristics of the behavior of the absolute error for different initializations. A comparison table between the traditional optimal relative error results and the absolute error ones is provided.

Two classes of systolic architectures are presented that are able to compute bicubical B-spline or Bezier polynomial coefficients and carry out polynomial evaluations. Using a pair of full arrays it is possible to compute all the coefficients in parallel, and to evaluate the polynomials for a given surface, as well as provide a speedup factor of more than 1500 compared with the single processor computation. An alternative solution is to partition both tasks into smaller sub-tasks so that a reduced size of the array is required. This allows a reasonable tradeoff between the speed needs and the VLSI implementation requirements to be achieved.

A general discussion on nonrestoring square root algorithms is presented, showing bounds and constraints delimiting the space of feasible algorithms, for all the choices of radix, digit set and representation of the partial remainder. Two classes of algorithms are then derived from the general discussion, and it is shown how it is possible to determine two parameters with a relevant impact on the implementation: the number of radicand bits to be inspected in order to obtain a starting value, and the number of partial remainder bits to be examined for digit selection. The algorithms for the specific case of radix 4 digit set {-2, -1, 0, +1, +2}, and partial remainder represented in carry-save form are derived in order to show that the algorithms introduced can lead to better results than those obtained with algorithms previously presented

Minimum requirements for the high-priority token holding time (HPTHT) in a network using timed token access protocols (such as IEEE 802.4 and FDDI) are derived in order to ensure that the throughput of synchronous messages is no lower than the amount of traffic generated for that class. The minimal value is essential in order to avoid unbounded queue length for the synchronous class as well as to achieve high network responsiveness. The results have been obtained for synchronous messages generated according to a generic periodic pattern with no constraint for the shape and for the period of the pattern. The manner in which the theoretical results obtained can be used to tune the network performance is also shown

Timed-token protocols are used to handle, on the same local area network, both real-time and non-real-time traffic. The authors analyze this type of protocol, giving worst-case values for the throughput of non-real-time traffic and the average token rotation time. Results are obtained for synchronous traffic generated according to a generic periodic pattern under heavy conditions for non-real-time traffic and express not only theoretical lower bounds but values deriving from the analysis of some real networks. A model which addresses the asynchronous overrun problem is presented. The influence of introducing multiple priority classes for non-real-time traffic on the total throughput of this type of message is shown. It is also shown that the differences between the values obtained under worst-case assumptions are close to those obtained under best-case assumptions; the method may therefore be used to provide important guidelines in properly tuning timed-token protocol parameters for each specific network installation

An architecture based on the Inmos T800 transputer is presented in this paper that is able to compute the bicubical polynomial coefficients for surfacesmodeling in computer graphics. The Occam tasks for the Bezier surfacemodelingalgorithm are discussed, both in the case of a full array, consisting of 256 transputers, and for a partitioned solution using 16 T800's. In particular, the problem of assigning the different tasks to the processors has been considered, showing how our solution can be easily tailored to the hardware resources available.

Division is one of the basic arithmetic operations supported by every computer system. The operation can be performed and implemented in either hardware or software, or a combination of the two. Although division is not as frequent as addition and multiplication, nowadays most processors implement it in hardware to not compromise the overall computation performances. In this note, we explain the basic algorithms, suitable for hardware and software, to implement division in computer systems. Two classes of algorithms implement division or square root: digit-recurrence and multiplicative (e.g., Newton-Raphson) algorithms. The first class of algorithms are of digit-recurrence type, and are especially suitable for hardware implementation as they require modest resources and provide good performance on contemporary technology. The second class of algorithms, multiplicative type, requires significant hardware resources and is more suitable for software implementation on the existing multiply units. The purpose of this note is to provide an introductory survey using a presentation style suitable for reading also by the interested non-specialist Readers.

The goal of desktop-class graphics hardware is generally to provide the maximum performances possible to end users. This goal is shared also by mobile hardware designers, although, due the use of a battery as power source, a greater attention needs to be devoted to energy saving. In the last years, a number of approaches to hardware design have been experimented aimed to trade-off the quality of the visual experience with the usage of computational resources, that is to say, with energy consumption. The objective of this work is to tackle energy issues at the software, i.e., at the application level, by introducing a high-level library based on OpenGL ES (often abbreviated GLES) that can be exploited by developers to create energy-aware graphics applications letting end users chose the maximum amount of energy to consume.

The increasing popularity of unmanned aerial vehicles (UAVs) in critical applications makes supervisory systems based on the presence of human in the control loop of crucial importance. In UAV-traffic monitoring scenarios, where human operators are responsible for managing drones, systems flexibly supporting different levels of autonomy are needed to assist them when critical conditions occur. The assessment of UAV controllers' performances thus their mental workload may be used to discriminate the level and type of automation required. The aim of this paper is to build a mental-workload prediction model based on UAV operators' cognitive demand to support the design of an adjustable autonomy supervisory system. A classification and validation procedure was performed to both categorize the cognitive workload measured by ElectroEncephaloGram signals and evaluate the obtained patterns from the point of view of accuracy. Then, a user study was carried out to identify critical workload conditions by evaluating operators' performances in accomplishing the assigned tasks. Results obtained in this study provided precious indications for guiding next developments in the field.

Approximate high radix dividers (HR-AXDs) are proposed and investigated in this paper. High-radix division is reviewed and inexact computing is introduced at different levels. Design parameters such as number of bits (N) and radix (r) are considered in the analysis; the replacement of exact cells with inexact cells in a binary signed-digit adder is introduced by utilizing different replacement schemes. Cell truncation and error compensation are also proposed to further extend inexact computation. Circuit-level performance and the error characteristics of the inexact high radix dividers are analyzed for the proposed designs. The combined assessment of the normal error distance, power dissipation and delay is investigated and applications of approximate high-radix dividers are treated in detail. The simulation results show that the proposed approximate dividers offer extensive saving in terms of power dissipation, circuit complexity and delay, while only incurring in a small degradation in accuracy thus making them possibly suitable and interesting to some applications and domains such as low power/mobile computing.

Using digital instruments to support artistic expression and creativity is a hot topic. In this work, we focused on the design of a suitable interface for Augmented Reality-based constructive art on handheld devices. Issues to be faced encompassed how to give artists sense of spatial dimensions, how to provide them with different tools for realizing artworks, and how much moving away from ``the real'' and going towards ``the virtual''. Through a touch-capable device, such as a smartphone or a tablet, we offer artists a clean workspace, where they can decide when to introduce artworks and tools. In fact, besides exploiting the multi-touch functionality and the gyroscopes/accelerometers to manipulate artworks in six degrees of freedom (6DOF), the proposed solution exploits a set of printed markers that can be brought into the camera's field of view to make specific virtual tools appear in the augmented scene. With such tools, artists can decide to control, e.g., manipulation speed, scale factor, scene parameters, etc., thus complementing functionalities that can be accessed via the device's screen.

The continuous progress in the field of robotics and the diffusion of its related application scenarios in today's modern world makes human interaction and communication with robots an aspect of fundamental importance. The development of interfaces based on natural interaction paradigms is getting an increasingly captivating topic in Human-Robot Interaction (HRI), due to their intrinsic capabilities in providing ever more intuitive and effective control modalities. Teleoperation systems require to handle a non-negligible amount of information coming from on-board sensors as well as input devices, thus increasing the workload of remote users. This paper presents the design of a 3D User Interface (3DUI) for the control of teleoperated robotic platforms aimed at increasing the interaction efficiency. A hand gesture driven controller is used as input modality to naturally map the position and gestures of the user's hand to suitable commands for controlling the platform components. The designed interface leverages on mixed reality to provide a visual feedback to the control commands issued by the user. The visualization of the 3DUI is superimposed to the video stream provided by an on-board camera. A user study confirmed that the proposed solution is able to improve the interaction efficiency by significantly reducing the completion time for tasks assigned in a remote reach-and-pick scenario.

A 3D User Interface for manipulating virtual objects in Augmented Reality scenarios on handheld devices is presented. The proposed solution takes advantage of two interaction techniques. The former (named ``cursor mode'') exploits a cursor, which position and movement are bound to the view of the device; the cursor allows the user to select objects and to perform coarse-grain manipulations by moving the device. The latter (referred to as ``tuning mode'') uses the physical affordances of a tangible interface to provide the user with the possibility to refine objects in all their aspects (position, rotation, scale, color, and so forth) with a fine-grained control

The paper presents a methodology for the automatic abstraction of analog magnetic components to achieve efficient simulation of complex smart system virtual platform. We aim at facilitating the validation process by allowing the simulation of both functional and extra-functional behaviors of the system with an unified simulation environment. The approach employs a process of simplification which removes unnecessary details of the analog model, enabling a much faster simulation.

Motion capture systems provide an efficient and interactive solution for extracting information related to a human skeleton, which is often exploited to animate virtual characters. When the character can- not be assimilated to an anthropometric shape, the task to map mo- tion capture data onto the armature to be animated could be extremely challenging. This paper presents a novel methodology for the automatic mapping of a human skeleton onto virtual character armatures. By ex- tending the concept of graph similarity, joints and bones of the tracked human skeleton are mapped onto an arbitrary shaped armature. A pro- totype implementation has been developed by using the Microsoft Kinect as body tracking device. Preliminary results show that the proposed so- lution can already be used to animate truly different characters such as a Pixar-like lamp, a fish or a dog.

Big Data is today both an emerging research area and a real present and future demand. High Performance Computing (HPC) Centers cannot neglect this fact and have to be reshaped to fulfill this need. In this paper we share our experience of upgrading a HPC Center at Politecnico di Torino, originally designed and deployed in 2010. We believe that this issue could be common to some other existing \"general purpose\" HPC centers where, at least in the short term, the possibility to start from scratch a new Big Data HPC center cannot be afforded but a balanced upgrade of the existing system has to be preferred

After an era of \"personal-computers-only\", supercomputing facilities and services are coming back to Universities to support research activities and computationally intensive simulations, but with some important differences with respect to the past. Besides the technological issues, while in the seventies-eighties the scene was dominated by mainframes, managed by skilled system managers and most of times used by operators with good computer expertise, today, the widespread and pervasive use of computers has lead to a completely different scenario. The demand for computation resources is emerging from a wide variety of areas and disciplines and mostly by users with basic expertise in computers, who however most of times request to have full control of the computation resources. Within this picture and especially at University level, High Performance Computing (HPC) has emerged as a good tradeoff to meet the different demands, and at the same offering good services at reasonable setup and maintenance costs. Traditionally, HPC has been and is being mostly used in support to applied research, but more recently some questions have emerged: - How much is it reasonable to offer HPC also to some teaching activities? What are the problems, advantages, and drawbacks? Is this the \"right\" way or should HPC resources be directed to research only? At Politecnico di Torino we tried to respond to these questions and started a test project called HPC-4-teaching. In this paper we present the results achieved by this project on a small set of courses during one full academic year

Computationally intensive applications often require the employment of parallel/distributed solutions in order to strongly reduce execution times. Workstations and PCs connected by a fast local network provide effective, low-cost, and general purpose solutions that are quickly replacing special purpose proprietary architectures for a wide spectrum of disciplines. The issue to monitor the performance (fundamental to check the efficiency of a distributed application) of cluster architectures is addressed in this work. This paper presents a multi-channel architecture for remote monitoring-management tailored to display information on PDA devices. Users can remotely monitor the system critical activities and cluster resources utilization; moreover, we provide the possibility to perform some management tasks (for instance, shutdown and reboot) useful for maintaining the integrity of the system and to harness the full cluster potential.

Several algorithms can effectively represent vector fields by texture-based representations, visualizing at most all information on the field: direction, orientation, and local magnitude. An open problem still remains the mapping on textures of adjunctive information such as temperature, pressure, and so on, without using colors. This article addresses this issue by proposing a technique to add a scalar value denoting streamlines by means of different levels of contrast. Both streamline starting tones and the range of tones depend on the scalar value to be mapped; in this way, areas visualized by different contrast levels are represented. Two examples show the effectiveness of the proposed technique

In recent years, virtual reality has shown all its potential in a large spectrum of applications: training, simulation, CAD, and so on. Although existing technologies allow the creation of immersive virtual reality browsing experiences, little has been devoted to applying this new tool to electronic commerce (e-commerce) since almost all e-commerce web sites present products in a 2D on-line catalog. In this paper we present 3D-dvshop, a dynamic 3D virtual shop: a user can build his or her own shop, choosing a set of products that will be dynamically placed in a collection of specially created \"rooms\". The use of technologies such as VRML and Java allows full 3D interaction with products. In this way, the browsing experience can be more natural, attractive, realistic, and fun

Visualization of vector data produced from application areas such as computational fluid dynamics (CFD), environmental sciences, and material engineering is a challenging task. Texture-based methods reveal to be e ective, versatile, and suitable for a large spectrum of applications since they allow to obtain high resolution output textures where direction, orientation, and magnitude of the ow can be displayed. In this paper we present a new method called B 2 LIC, which allows both to characterize and visualize interesting structures in the ow and to map two additional scalar values in output textures by bumps, depressions, and shadows, leaving colors for further information mapping. B 2 LIC is the natural and direct evolution and the improvement of the BLIC (Bumped LIC) algorithm, which is able to map just one scalar value by the bump mapping technique. Some examples show how the proposed method can e ectively allow to map two additional scalar values such as: temperature, vorticity, pressure, and so on, adding new and additional representation capabilities to dense texture-based visualization methodologies.

An extension of the very-high radix division with prescaling and selection by rounding is presented. This extension consists in increasing the effective radix of the implementation by obtaining a few additional bits of the quotient per iteration, without increasing the complexity of the unit to obtain the prescaling factor nor the delay of an iteration. As a consequence, for some values of the effective radix, it permits an implementation with a smaller area and the same execution time than the original scheme. Estimations are given for 54-bit and 114-bit quotients.

We present a new and efficient algorithm to generate rendered animation. With respect to the approaches known in the existing literature, our algorithm does not generate the animated sequences frame-by-frame, but it renders only the parts which change between two following frames by exploiting the frame-to-frame coherence. We show, with practical examples, the efficiency of the proposed technique. In the proposed examples the animation can be rendered, with our method, at least eight times faster than by using a straightforward frame-by-frame technique

An algorithm for square root with prescaling is developed and combined with a similar scheme for division. An implementation is described, evaluated and compared with other combined div/sqrt implementations

A division algorithm in which the quotient-digit selection is performed by rounding the shifted residual in carry-save form is presented. To allow the use of this simple function, the divisor (and dividend) is prescaled to a range close to one. The implementation presented results in a fast iteration because of the use of carry-save forms and suitable recodings. The execution time is calculated, and several convenient values of the radix are selected. Comparison with other high-radix dividers is performed using the same assumptions

The authors consider the possibility of designing architectures which combine in the best possible way the convergence with the square advantages of the Newton-Raphson method with the precision characteristics of the digit-by-digit algorithms so as to obtain units which satisfy the IEEE 754 floating point standard requirements. This is a general method which can be extended with simple and minor changes also to square root. Attention is focused on a possible implementation of this design methodology for division. The evaluation shows that the proposed unit offers an alternative architecture for division which provides interesting performances

A study of the throughput and time characteristics of double-ring networks is presented, assuming that the two channels are used for balancing the traffic (when both are working) and for synchronous traffic generated according to a generic but periodic pattern. In addition, reconfiguration using portions of both rings to circumvent faulty elements in a double ring network is shown to be equivalent to the single ring configuration already studied. Examples of applications of the results are also illustrated

A general approach is outlined for designing units for higher radix division, which are based on two subunits operating in parallel. A lower radix division unit is used as the building block of the architecture, and the division step is split into two phases which are carried out in parallel. It is shown that the proposed architecture permits the design of units for higher radix division with digit selection tables requiring few supplementary input bits compared to the tables used by lower radix division systems